The present invention relates to semiconductor devices and methods of fabricating the same, and more particularly, to semiconductor devices having recessed gate electrodes and methods of fabricating the same.
As electronic products employing semiconductor devices have become increasingly thin, lightweight, and compact, semiconductor devices used in such produce generally have been required to become more highly integrated. Accordingly, research for reducing the two-dimensional size of transistors has been ongoing.
Reduction in transistor size may lead to a reduction in channel length and channel width. Drive current of a transistor is generally inversely proportional to the channel length, and generally is proportional to the channel width. A reduction in channel length may increase the drive current and response speed. In contrast, the reduction in channel length may cause problems, such as punch-through. Consequently, there is a continuing need for technology for minimizing the two-dimensional size of transistors while providing an effective channel length.
A configuration known as a recess channel array transistor (RCAT) has been proposed to increase effective channel length. A gate trench is formed within an active region of the RCAT. An insulated gate electrode fills the gate trench and crosses the active region. The gate trench may act to increase the effective channel length.
Another configuration referred to as a spherical recess channel array transistor (SRCAT) has been proposed to increase effective channel length. An upper gate trench is formed within an active region of the SRCAT. A lower gate trench is formed in the shape of a flask below the upper gate trench. An insulated gate electrode fills the upper and lower gate trenches and crosses the active region. The upper and lower gate trenches may increase the effective channel length.
A reduction in channel width typically decreases the drive current. Generally, channel width is designed in consideration of the drive current required for the operation of the semiconductor device. Accordingly, techniques that extend effective channel width may be advantageous in terms of the reduction in transistor channel width.
FIG. 1 is a cross-sectional view of a conventional RCAT. A first region 1 of FIG. 1 is a cross-section of the RCAT in a word line direction, and a second region 2 of FIG. 1 is a cross-section of the RCAT in a bit line direction. Referring to FIG. 1, the conventional RCAT has an isolation layer 16 defining an active region 13 within a semiconductor substrate 11. The isolation layer 16 may include a sidewall oxide layer 14 and an insulating layer 15, which are stacked. A gate trench 17 is formed in the active region 13. The gate trench 17 crosses the active region 13 and partially exposes sidewalls of the isolation layer 16. A gate electrode 19 is formed across the active region 13. The gate electrode 19 has a gate electrode 19E extending into the gate trench 17. A gate dielectric layer 18 is interposed between the active region 13 and the gate electrode 19. The gate dielectric layer 18 is also interposed between the active region 13 and the gate electrode 19E. Source and drain regions 21 and 23 are formed within the active region 13 at respective sides of the gate electrode 19.
An effective channel length CL1 of the RCAT is relatively long compared to a planar transistor because of the gate trench 17. Accordingly, even when the two-dimensional size of the RCAT is reduced, a desirable effective channel length CL1 may be secured.
However, an effective channel width CW1 of the RCAT may be dependent on the size of the active region 13. The active region 13 is defined by the isolation layer 16. In the illustrated device, to reduce the two-dimensional size of the RCAT, it may be advantageous to reduce the active region 13 to a resolution limit of a photolithography process. The reduction in active region 13 may cause the effective channel width CW1 to be reduced. In this case, current drivability of the RCAT may be reduced.
The width of the active region 13 may be increased to increase the effective channel width CW1. However, this approach may work against high integration of the RCAT.
Another technique for increasing effective channel width is described in U.S. Patent Publication No. 2003/0085435 to Wang entitled “Transistor Structure and Process to Fabricate Same.” According to this published application, at least one recess region is formed in a channel length direction of an active region. An insulated gate electrode is formed across the recess regions. The recess regions act to extend the effective channel width of the transistor. Another technique for forming a transistor is described in U.S. Pat. No. 6,844,591 to Tran entitled “Method of Forming DRAM Access Transistors.”
There is an ongoing need for techniques for reducing transistor size while providing desirable effective channel width.